An input receiver (e.g., a low voltage complementary metal oxide semiconductor (LVCMOS) receiver) downconverts an external signal (e.g., a pad signal) at an input/output (I/O) supply voltage level to feed the downconverted signal to the core of a semiconductor chip at a required voltage level. Currently, the input receiver employs an inverter or buffer like architecture which fixes its dc trip point based on the size of the input receiver. Thus, if the external signal of the input receiver is greater than the dc trip point, then it is converted to the supply voltage level of the input receiver, whereas if the external signal is less than the dc trip point, then it is converted to zero voltage.
The input receiver may be built with a hysteresis to compensate for noise in the external signal. Thus, when the output of the hysteresis input receiver is in a low state (e.g., 0 volt), the output of the hysteresis input receiver transitions from the low state to a high state only if the external voltage is greater than a positive DC trip point, which is the reference voltage increased by a positive (low state-to-high state transitioning) threshold voltage. Likewise, when the output of the hysteresis input receiver is in the high state, the output of the hysteresis input receiver transitions from the high state to the low state only if the external voltage is less than a negative DC trip point, which is the reference voltage decreased by a negative (high state-to-low state transitioning) threshold voltage.
The arrangement for the hysteresis input receiver may work well when the I/O supply voltage level (e.g., 1.8 volts) is equal or less than the maximum voltage (e.g., 1.8 volts) that low voltage transistors in the hysteresis input receiver can sustain. However, for higher I/O supply voltage levels (e.g., 2.5 volts or 3.3 volts) greater than the maximum voltage (e.g., 1.8 volts) that the low voltage transistors can sustain, the design may stress the low voltage transistors, thereby degrading performance of the hysteresis input receiver. For example, the design of the hysteresis input receiver may have to be heavily skewed to meet the LVCMOS joint electron device engineering council (JEDEC) switching thresholds for higher supply voltages (e.g., 3.3 volts), and the distortion in the design of the hysteresis input receiver may degrade the receiver's performance.